Novel Circuit-Level Model for Gate Oxide Short and its Testing Method in SRAMs
Novel Circuit-Level Model for Gate Oxide Short and its Testing Method in SRAMs
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SRAM中栅氧化层短路的新型电路级模型及其测试方法
DOI:
10.1109/tvlsi.2013.2268984
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发表时间:
2014
影响因子:
2.8
通讯作者:
Chih
中科院分区:
文献类型:
--
作者:
Chen;M. Chao;Chih
Gate oxide short (GOS) has become a common defect for advanced technologies as the gate oxide thickness of a MOSFET is greatly reduced. The behavior of a GOS-impacted MOSFET is, however, complicated and difficult to be accurately modeled at the circuit level. In this paper, we first build a golden model of a GOS-impacted MOSFET by using technology CAD, and identify the limitation and inaccuracy of the previous GOS models. Next, we propose a novel circuit-level GOS model which provides a higher accuracy of its dc characteristics than any of the previous models and being is able to represent a minimum-size GOS-impacted MOSFET. In addition, the proposed model can fit the transient characteristics of a GOS by considering the capacitance change of the GOS-impacted MOSFET, which has not been discussed in previous work. Last, we utilize our proposed GOS model to develop a novel GOS test method for SRAMs, which can effectively detect the GOS defects usually escaped from the conventional IDDQ test and March test.