Symbol-Level Detection With Matched Non-Binary LDPC Codes for Position Errors in Racetrack Memories
Symbol-Level Detection With Matched Non-Binary LDPC Codes for Position Errors in Racetrack Memories
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DOI：
10.1109/tmag.2022.3214932
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发表时间：
2023-02
影响因子：
2.1
通讯作者：
Ryo Shibata;H. Yashima
中科院分区：
文献类型：
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作者：
Ryo Shibata;H. Yashima
在赛马场存储器（RM）中，由于排列错误导致插入和删除（ID）错误；这种误差被称为位置误差（pe）。近年来，人们提出了几种基于二进制低密度奇偶校验（BI-LDPC）码的pe编码方案，并采用联合比特检测和解码算法。虽然这些方案产生了有希望的渐近性能，但它们在短块大小下的有限长度性能令人不满意。为了解决这个问题，我们提出了一种基于非二进制LDPC （NB-LDPC）编码和符号检测的新编码方案。该方案的因子图利用了RM同时由pe引起多个ID错误的特殊性质，避免了在检测器和解码器图之间产生循环，从而在提供快速收敛的同时获得了良好的有限长性能。为了进一步提高性能，我们还提供了一个SW外部信息传输图分析来设计NB-LDPC代码。
In racetrack memory (RM), insertion and deletion (ID) errors occur owing to alignment faults; such errors are referred to as position errors (PEs). Recently, several coding schemes for PEs have been proposed based on binary low-density parity-check (BI-LDPC) codes with a joint bit-wise (BW) detection and decoding algorithm. Although these schemes yield promising asymptotic performance, they suffer from unsatisfactory finite-length performance in short block sizes. To address this problem, we propose a novel coding scheme based on non-binary LDPC (NB-LDPC) codes and symbol-wise (SW) detection. The factor graph of the proposed scheme avoids generating cycles between the detector and decoder graphs by leveraging RM’s special property that multiple ID errors are caused by PEs simultaneously, which enables the attainment of good finite-length performance while providing fast convergence. With the aim of providing further performance improvement, we also provide an SW extrinsic information transfer chart analysis to design NB-LDPC codes for the proposed scheme.