Thermal resilient bounded-skew clock tree optimization methodology
Thermal resilient bounded-skew clock tree optimization methodology
复制标题
热弹性有界偏斜时钟树优化方法
DOI：
10.1109/date.2006.243740
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发表时间：
2006
期刊：
影响因子：
--
通讯作者：
M. Poncino
中科院分区：
文献类型：
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作者：
A. Chakraborty;P. Sithambaram;K. Duraisami;A. Macii;E. Macii;M. Poncino
高性能 IC 基板上存在的不均匀热梯度会显着影响全局片上互连的性能。激进的扩展和其他因素（例如动态电源管理方案和不均匀的门级开关活动）进一步加剧了这个问题。在高性能系统中，最重要的问题之一是时钟偏差最小化，因为它直接影响系统的最大工作频率。由于时钟在整个芯片上布线，因此热梯度的存在会显着改变其特性，因为导线电阻随着温度的升高而线性增加。这通常会导致无法满足原始时序约束，从而导致原始拓扑无法使用。因此，有必要对原始拓扑进行温度感知重新嵌入，以满足这些温度影响下的时序要求。这项工作主要通过提出两种算法来探索这些问题，这两种算法可以重新构建现有的时钟树拓扑，以补偿此类温度影响，从而满足时序约束
The existence of non-uniform thermal gradients on the substrate in high performance IC's can significantly impact the performance of global on-chip interconnects. This issue is further exacerbated by the aggressive scaling and other factors such as dynamic power management schemes and non-uniform gate level switching activity. In high-performance systems, one of the most important problems is clock skew minimization since it has a direct impact on the maximum operating frequency of the system. Since clocks are routed across the entire chip, the presence of thermal gradients can significantly alter their characteristics because wire resistance increases linearly as the temperature increases. This often results in failure to meet original timing constraints thereby rendering the original topology unusable. Therefore it is necessary to perform a temperature aware re-embedding of the original topology to meet timing under these temperature effects. This work primarily explores these issues by proposing two algorithms that re-structure an existing clock tree topology to compensate for such temperature effects and as a result also meet timing constraints