Buffered Hash Table: Leveraging DRAM to Enhance Hash Indexes in the Persistent Memory
Buffered Hash Table: Leveraging DRAM to Enhance Hash Indexes in the Persistent Memory
复制标题
DOI：
10.1109/nvmsa56066.2022.00011
复制
发表时间：
2022-08
期刊：
影响因子：
--
通讯作者：
Chen Zhong;Prajwal Challa;Xingsheng Zhao;Song Jiang
中科院分区：
文献类型：
--
作者：
Chen Zhong;Prajwal Challa;Xingsheng Zhao;Song Jiang
作为类似于DRAM的高速字节可调的存储介质，英特尔Optane DC持久记忆（PMEM）引起了研究社区的兴趣，因为其高吞吐量和低潜伏期。这些属性推动了DRAM数据结构（例如哈希表）的迁移到PMEM。但是，现有的PMEM哈希表设计并不意识到PMEM也是一个块设备，访问单元为256个字节。因此，他们执行的写作尺寸比PMEM访问单元小的数量级，从而导致高写入放大。为了提高其性能，我们提出了缓冲的哈希表（BHT）设计。 BHT将多个写入DRAM缓冲区批量写入，然后将它们合并到PMEM中的哈希表格中，从而减少了小写入的数量。 BHT还采用基于PMEM的Writeahead日志来防止数据丢失。我们的实验表明，BHT提供了高达2.3倍和2.8倍更高的写入吞吐量，假设与Art-Art-Art-Art Hash索引（即CCEH和DASH）相比，DRAM空间足够可用。
As a high-speed byte-addressable storage media similar to DRAM, Intel Optane DC Persistent Memory (PMem) has drawn the interest from the research community for its high throughput and low latency. These properties propel the migration of in-DRAM data structures, such as hash tables, to the PMem. However, existing PMem hash table designs do not recognize that the PMem is also a block device with an access unit of 256 bytes. Consequently, they carry out writes in sizes that are an order of magnitude smaller than the PMem access unit, leading to high write amplification. To improve their performance, we propose Buffered Hash Table (BHT) design. BHT batches multiple writes into in-DRAM buffers and then merges them into hash table buckets in the PMem, reducing the number of small writes. BHT also employs a PMem-based writeahead log to prevent data loss. Our experiments show that BHT provides up to 2.3X and 2.8X higher write throughput, assuming the DRAM space is sufficiently available, compared to the stateof-the-art hash indexes, namely CCEH and Dash, respectively.