Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations
Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations
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DOI：
10.1109/iccad.2005.1560162
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发表时间：
2005-05
期刊：
影响因子：
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通讯作者：
A. Agarwal;Kunhyuk Kang;K. Roy
中科院分区：
文献类型：
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作者：
A. Agarwal;Kunhyuk Kang;K. Roy
在本文中，我们提出了一种准确的电路总泄漏分布的估计和建模，同时考虑了芯片间和芯片内的变化(L的变化、T/SUBOX/和随机掺杂波动)。由于电路中的总泄漏取决于晶体管中的泄漏、逻辑门中晶体管的集成度以及电路块中的门拓扑，因此我们在考虑晶体管、逻辑门、电路拓扑和输入矢量之间的不同相关性的同时，对电路设计中各级电路中的总泄漏分布进行建模。该模型准确地估计了泄漏分布的统计信息(均值和方差)和形状。利用有效长度为50 nm的器件对模型进行了蒙特卡罗模拟验证，并对结果进行了分析，列举了不同工艺参数对总漏电流各分量的影响。
In this paper we propose an accurate estimation and modeling of total circuit leakage distribution, considering both inter- and intra-die variations (variation in L, T/sub ox/ and random dopant fluctuation). Since, the total leakage in a circuit depends on leakage in a transistor, integration of transistors in a logic gate, and the gate topology in a circuit block, we model the total circuit leakage distribution at all levels of circuit design, while taking the different correlations among transistors, logic gates, circuit topology, and input vectors into account. The proposed model accurately estimates both statistical information (mean and variance) and the shape of the leakage distribution. We have verified the model using Monte Carlo simulation using devices of 50nm effective length and analyzed the results to enumerate the effect of different process parameters on individual components of total leakage.