Energy-efficient signal processing via algorithmic noise-tolerance

Energy-efficient signal processing via algorithmic noise-tolerance
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通过算法抗噪实现节能信号处理

DOI:
10.1145/313817.313834
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发表时间:
1999
期刊:
Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477)
影响因子:
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通讯作者:
Naresh R Shanbhag
Naresh R Shanbhag
中科院分区:
--
文献类型:
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作者:
R. Hegde;Naresh R Shanbhag

文献摘要

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在本文中,我们提出了一个低功耗数字信号处理(DSP)的框架,其中电源电压的比例超过临界电压所需的关键路径延迟的吞吐量相匹配。这种故意引入依赖于输入的误差导致算法性能的下降,这是通过算法噪声容限(ANT)方案进行补偿。由在亚临界电压下操作的DSP架构和误差控制方案组成的结果设置被称为软DSP。结果表明,技术缩放使所提出的方案更有效的延迟惩罚所遭受的电压缩放减少由于短沟道效应。当采用具有更高“延迟不平衡”的算术单元时,所提出的方案的有效性也得到了增强。提出了一种基于预测的误差控制方案,以提高滤波算法在软计算误差情况下的性能。对于频率选择性滤波器,它示出,所提出的方案提供了60%-81%的能量耗散的滤波器带宽高达0.5 /spl π/(其中2 /spl π/对应于采样频率f/sub s/)通过传统的电压缩放实现的,与最大的0.5 dB的输出信噪比(SNR/sub o/)的退化。它还表明,所提出的算法的噪声容限计划可以用来提高DSP算法的性能,在存在的位错误率高达10/sup-3/由于深亚微米(DSM)噪声。
In this paper, we propose a framework for low-energy digital signal processing (DSP) where the supply voltage is scaled beyond the critical voltage required to match the critical path delay to the throughput. This deliberate introduction of input-dependent errors leads to degradation in the algorithmic performance, which is compensated for via algorithmic noise-tolerance (ANT) schemes. The resulting setup comprised of the DSP architecture operating at sub-critical voltage and the error control scheme is referred to as soft DSP. It is shown that technology scaling renders the proposed scheme more effective as the delay penalty suffered due to voltage scaling reduces due to short channel effects. The effectiveness of the proposed scheme is also enhanced when arithmetic units with a higher "delay-imbalance" are employed. A prediction based error-control scheme is proposed to enhance the performance of the filtering algorithm in presence of errors due to soft computations. For a frequency selective filter, it is shown that the proposed scheme provides 60%-81% reduction in energy dissipation for filter bandwidths up to 0.5 /spl pi/ (where 2 /spl pi/ corresponds to the sampling frequency f/sub s/) over that achieved via conventional voltage scaling, with a maximum of 0.5 dB degradation in the output signal-to-noise ratio (SNR/sub o/). It is also shown that the proposed algorithmic noise-tolerance schemes can be used to improve the performance of DSP algorithms in presence of bit-error rates of up to 10/sup -3/ due to deep submicron (DSM) noise.