Use of Commercial FPGA-Based Evaluation Boards for Single-Event Testing of DDR2 and DDR3 SDRAMs
Use of Commercial FPGA-Based Evaluation Boards for Single-Event Testing of DDR2 and DDR3 SDRAMs
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DOI：
10.1109/tns.2013.2285517
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发表时间：
2013-12
影响因子：
1.8
通讯作者：
Raymond L. Ladbury;M. Berg;E. P. Wilcox;K. Label;Hak Kim;A. Phan;C. Seidleck
中科院分区：
文献类型：
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作者：
Raymond L. Ladbury;M. Berg;E. P. Wilcox;K. Label;Hak Kim;A. Phan;C. Seidleck
DDR2和DDR3 SDRAM的速度、严格的时序要求和复杂的错误行为给单事件测试带来了巨大的挑战。通常，每一代新产品都需要昂贵的新测试仪，并配备最先进的内存控制器。我们探讨了使用基于FPGA的商用评估板进行DDR2和DDR3 SDRAM辐射测试的利弊。我们评估由此产生的数据质量，并讨论测试仪的性能，同时也阐明和比较SEE兼容性DDR2和DDR3 SDRAM。
The speed, tight timing requirements packaging and complicated error behavior of DDR2 and DDR3 SDRAMs pose significant challenges for single-event testing. Often, each new generation will require an expensive new tester with a state-of-the-art controller for the memory. We explore the trade-offs in the use of commercial FPGA based evaluation boards for radiation testing DDR2 and DDR3 SDRAMs. We evaluate the resulting data quality and discuss tester performance while also elucidating and comparing SEE susceptibilities in DDR2 and DDR3 SDRAMs.