Implementation of Self-Timed Circuits onto FPGAs Using Commercial Tools
Implementation of Self-Timed Circuits onto FPGAs Using Commercial Tools
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使用商业工具在 FPGA 上实现自定时电路
DOI：
10.1109/dsd.2008.73
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发表时间：
2008
期刊：
影响因子：
--
通讯作者：
L. Reyneri
中科院分区：
文献类型：
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作者：
M. Tranchero;L. Reyneri
近年来，异步设计变得越来越流行。许多工具和设计方法已经开发出这种电路。不幸的是，只有少数人专注于在fpga上的实现。如今，fpga在许多应用中广泛应用，它们具有足够的复杂性，可以进行原型设计和复杂设计。因此，本文的重点是使用传统工具和流程在可编程设备上实现特定于异步的块。它提供了在fpga上实现Muller C元件和延迟链的解决方案，避免了合成和拟合阶段给出的不必要的行为。本文还介绍了在我们的协同设计环境中采用的自动生成用于异步电路单轨实现的延迟链的解决方案。这是我们项目的一部分，旨在开发一个完整的框架，用于从Simulink模型中生成异步电路。
Asynchronous design has become more and more popularin last years. Many tools and design methodologies have been developed for this kind of circuits. Unfortunately only few of them are focused on their implementation onto FPGAs. Nowadays FPGAs are widespread in many applications and they have enough complexity to allow prototyping also complex designs. For this reason this paper is focused on the implementation of asynchronous-specific blocks on programmable devices using conventional tools and flows. It offers solutions for implementing Muller C elements and delay chains onto FPGAs avoiding unwanted behavior given by the synthesis and the fitting phases. This paper also introduces the solution adopted in our co-design environment to automatically generate delay chains used to single-rail implementation of asynchronous circuits. This is a part of our project which aims at developing a complete framework for producing asynchronous circuits from Simulink models.