The design of a low energy FPGA
The design of a low energy FPGA
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低功耗FPGA的设计
DOI：
10.1145/313817.313920
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发表时间：
1999
期刊：
影响因子：
--
通讯作者：
J. Rabaey
中科院分区：
文献类型：
--
作者：
G. Varghese;Hui Zhang;J. Rabaey
本文提出了一种节能的FPGA架构设计。通过同时解决电路设计和架构优化问题，可以显著降低能耗。采用了结合最近邻连接、对称网格结构和分层连接的混合互连结构。通过采用低摆幅电路技术，也降低了互连的能量。这些技术已被用于设计和制造FPGA。初步分析表明，与现有的商业建筑相比，能源改善超过一个数量级。
This work presents the design of an energy efficient FPGA architecture. Significant reduction in the energy consumption is achieved by tackling both circuit design and architecture optimization issues concurrently. A hybrid interconnect structure incorporating nearest neighbor connections, symmetric mesh architecture, and hierarchical connectivity is used. The energy of the interconnect is also reduced by employing low-swing circuit techniques. These techniques have been employed to design and fabricate an FPGA. Preliminary analysis show energy improvement of more than an order of magnitude when compared to existing commercial architectures.