Measuring the Gap Between FPGAs and ASICs
Measuring the Gap Between FPGAs and ASICs
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DOI：
10.1145/1117201.1117205
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发表时间：
2006-02
影响因子：
2.9
通讯作者：
Ian Kuon;Jonathan Rose
中科院分区：
文献类型：
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作者：
Ian Kuon;Jonathan Rose
本文通过实验测量了90纳米CMOS现场可编程门阵列（FPGA）和90纳米CMOS标准单元专用集成电路（ASIC）在逻辑密度、电路速度和核心逻辑功耗方面的差异。我们的动机是进行这些测量，使系统设计人员能够在这两种介质之间做出更明智的选择，并让FPGA制造商深入了解需要攻击的缺陷，从而改进FPGA。我们描述的方法，通过该方法获得的测量结果，并表明，对于只包含基于查找表的逻辑和触发器的电路，在FPGA和ASIC中实现它们所需的硅面积的比例平均为35。现代FPGA还包含“硬”模块，如乘法器/乘法器和块存储器。我们发现，这些块减少了这个平均面积差距显着小到18为我们的基准，我们估计，广泛使用这些硬块可能会降低差距低于5。从FPGA到ASIC的关键路径延迟之比大约为三比四，受块存储器和硬乘法器的影响较小。动态功耗比约为14倍，并且对于硬块，该间隙通常变得更小
This paper presents experimental measurements of the differences between a 90-nm CMOS field programmable gate array (FPGA) and 90-nm CMOS standard-cell application-specific integrated circuits (ASICs) in terms of logic density, circuit speed, and power consumption for core logic. We are motivated to make these measurements to enable system designers to make better informed choices between these two media and to give insight to FPGA makers on the deficiencies to attack and, thereby, improve FPGAs. We describe the methodology by which the measurements were obtained and show that, for circuits containing only look-up table-based logic and flip-flops, the ratio of silicon area required to implement them in FPGAs and ASICs is on average 35. Modern FPGAs also contain "hard" blocks such as multiplier/accumulators and block memories. We find that these blocks reduce this average area gap significantly to as little as 18 for our benchmarks, and we estimate that extensive use of these hard blocks could potentially lower the gap to below five. The ratio of critical-path delay, from FPGA to ASIC, is roughly three to four with less influence from block memory and hard multipliers. The dynamic power consumption ratio is approximately 14 times and, with hard blocks, this gap generally becomes smaller