Fast residue arithmetic multipliers based on signed-digit number system
Fast residue arithmetic multipliers based on signed-digit number system
复制标题
基于有符号数字系统的快速余数算术乘法器
DOI：
10.1109/icecs.2001.957730
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发表时间：
2001
期刊：
影响因子：
--
通讯作者：
K. Shimizu
中科院分区：
文献类型：
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作者：
Shugang Wei;K. Shimizu
提出了一种基于基2符号数（SD）的快速余数算术乘法器。对于给定的模m，2/supp/-1/spl les/m/spl les/ 2/supp/+2/supp-1/-1，在剩余数制（RNS）中，模m加法是用一个或两个p位SD加法器来完成的，模m加法的时间与操作数的字长无关。本文提出了两种模m乘法器，它们分别由模m SD加法器和加法器的二叉树构成，模m乘法分别在与p和log/sub 2/p成比例的时间内完成。16-用VHDL语言设计了一个数字余数算术乘法器电路，结果表明，该电路可以实现高速余数算术乘法器。
Fast residue arithmetic multipliers based on a radix-2 signed-digit (SD) number are presented. For a given modulus m, 2/sup p/-1/spl les/m/spl les/ 2/sup p/+2/sup p-1/-1, in a residue number system (RNS), the modulo m addition is performed by using one or two p-digit SD adders, and the modulo m addition time is independent of the word length of operands. We propose two kinds of modulo m multipliers which are constructed using a modulo m SD adder and a binary tree of the adders and the modulo m multiplication are performed in a time proportional to p and log/sub 2/p, respectively. 16-digit residue arithmetic multiplier circuits have been designed using VHDL, and the results show that high speed residue arithmetic circuits can be implemented.