A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited
复制标题
实现超越 CMOS 时代指数缩放的途径：受邀
DOI：
10.1145/3061639.3072942
复制
发表时间：
2017
期刊：
影响因子：
--
通讯作者：
R. Kawakami
中科院分区：
文献类型：
--
作者：
Jianping Wang;S. Sapatnekar;C. Kim;P. Crowell;S. Koester;S. Datta;K. Roy;A. Raghunathan;X. Hu;M. Niemier;A. Naeemi;C. Chien;C. Ross;R. Kawakami
我们社会的许多关键技术，包括所谓的人工智能（AI）和大数据，都是通过晶体管的发明及其不断减小的尺寸和不断增加的大规模集成实现的。然而，传统技术面临着明显的缩放限制。许多最近提出的先进晶体管概念在实验室中也面临着一场艰苦的战斗，因为必要的性能权衡和有限的扩展潜力。我们主张一种新的途径，可以使指数扩展多代。这条途径涉及分层的多种技术，使新的功能超出了传统和新提出的晶体管。这一新途径的关键原则已经通过C-SPIN（STARnet中心）的跨学科团队的努力得到了证明，系统设计师，设备制造商，材料科学家和物理学家都在一个保护伞下工作，以克服关键技术障碍。本文回顾了几个成功的成果，从这方面的努力主题，如自旋存储器，逻辑存储器，认知计算，随机和概率计算和可重构信息处理。
Many key technologies of our society, including so-called artificial intelligence (AI) and big data, have been enabled by the invention of transistor and its ever-decreasing size and ever-increasing integration at a large scale. However, conventional technologies are confronted with a clear scaling limit. Many recently proposed advanced transistor concepts are also facing an uphill battle in the lab because of necessary performance tradeoffs and limited scaling potential. We argue for a new pathway that could enable exponential scaling for multiple generations. This pathway involves layering multiple technologies that enable new functions beyond those available from conventional and newly proposed transistors. The key principles for this new pathway have been demonstrated through an interdisciplinary team effort at C-SPIN (a STARnet center), where systems designers, device builders, materials scientists and physicists have all worked under one umbrella to overcome key technology barriers. This paper reviews several successful outcomes from this effort on topics such as the spin memory, logic-in-memory, cognitive computing, stochastic and probabilistic computing and reconfigurable information processing.