RRAM-Based In-Memory Computing for Embedded Deep Neural Networks
RRAM-Based In-Memory Computing for Embedded Deep Neural Networks
复制标题
用于嵌入式深度神经网络的基于 RRAM 的内存计算
DOI：
10.1109/ieeeconf44664.2019.9048704
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
B. Murmann
中科院分区：
文献类型：
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作者：
Daniel Bankman;J. Messner;Albert Gural;B. Murmann
在嵌入式设备上部署最先进的深度神经网络 (DNN) 带来了重大的实施挑战，很大程度上是由于内存访问的能源成本。基于 RRAM 的内存处理单元 (IPU) 可实现完全分层流水线架构，最大限度地减少存储特征图所需的 SRAM 内存容量，并将其访问分摊到数百到数千次算术运算。本文提出了一种基于 RRAM 的 IPU，具有动态电压模式乘法累加和带有 RRAM 嵌入式斜坡发生器的单斜率 A/D 读出方案，它们共同消除了高功耗的电流模式电路，而不牺牲线性度。 SPICE仿真表明，这种基于RRAM的IPU架构可以实现高达1.2 2b-POps/s/W的阵列级能效和超过45 2b-TOps/s/mm2的面积效率。
Deploying state-of-the-art deep neural networks (DNNs) on embedded devices has created a major implementation challenge, largely due to the energy cost of memory access. RRAM-based in-memory processing units (IPUs) enable fully layerwise-pipelined architectures, minimizing the required SRAM memory capacity for storing feature maps and amortizing its access over hundreds to thousands of arithmetic operations. This paper presents an RRAM-based IPU featuring dynamic voltage-mode multiply-accumulate and a single-slope A/D readout scheme with RRAM-embedded ramp generator, which together eliminate power-hungry current-mode circuitry without sacrificing linearity. SPICE simulations suggest that this RRAM-based IPU architecture can achieve an array-level energy efficiency up to 1.2 2b-POps/s/W and an area efficiency exceeding 45 2b-TOps/s/mm2.