Data link design using a time-based approach

Data link design using a time-based approach
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使用基于时间的方法进行数据链路设计

DOI:
10.1109/iscas.2010.5537664
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发表时间:
2010
期刊:
Proceedings of 2010 IEEE International Symposium on Circuits and Systems
影响因子:
--
通讯作者:
B. Maundy
B. Maundy
中科院分区:
--
文献类型:
--
作者:
M. Rashdan;A. Yousif;J. Haslett;B. Maundy

文献摘要

被引文献

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描述了一种基于时间的SerDes数据传输方法。作为概念验证,2位800 Mbps和3位1.2 Gbps的基于时间的串行链路已设计和实施使用Altera收发器信号完整性开发FPGA套件。已测量并比较了两条链路的传输信号和40英寸FR4迹线末端信号的眼图。已在接收器侧成功地恢复了传输的代码。
A time-based approach to SerDes data transfer is described. As proof of concept, 2-bit 800 Mbps and 3-bit 1.2 Gbps time-based serial links have been designed and implemented using an Altera transceiver signal integrity development FPGA kit. The eye diagram of both the transmitted signal and the signal at the end of a 40-inch FR4 trace have been measured and compared for both links. The transmitted code has been successfully recovered at the receiver side.