Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.
Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.
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DOI：
10.1109/tcpmt.2011.2166395
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发表时间：
2011-12-01
期刊：
影响因子：
--
通讯作者：
Theogarajan L
中科院分区：
文献类型：
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作者：
Uddin A;Milaninia K;Chen CH;Theogarajan L
本文提出了一种将小型CMOS芯片集成到大面积衬底上的新技术。该技术的关键组成部分是基于CMOS芯片的自对准掩模。这允许在晶圆上制造最多比每侧芯片大5微米的插座。所述芯片和大面积基板粘合到载体上，使得所述两个组件的顶表面是齐平的。该技术的独特特性使其能够集成宏观元件，如引线和微流体。此外，集成过程允许在CMOS芯片集成后进行MEMS微加工。为了证明所提出的技术的能力，采用AMI 0.5µm CMOS技术实现的生物传感低功耗集成恒电位器芯片集成在硅衬底中。集成后测量的芯片与大面积衬底之间的水平间隙和垂直位移分别为4µm和0.5µm。104个互连点采用高精度校准模式。电气测量表明，芯片的功能不受集成过程的影响。
This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.