Design Automation of Series Resonance Clocking in 14-nm FinFETs
Design Automation of Series Resonance Clocking in 14-nm FinFETs
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DOI：
10.1007/s00034-023-02458-4
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发表时间：
2023-08
期刊：
影响因子：
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通讯作者：
Dhandeep Challagundla;Ignatius-In Bezzam;Riadul Islam
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文献类型：
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作者：
Dhandeep Challagundla;Ignatius-In Bezzam;Riadul Islam
在过去的二十年里，功率-性能限制一直是推动微处理器行业带来独特设计技术的关键驱动力。对高性能微处理器的需求不断增加，增加了电路的复杂性和数据传输率，导致了更高的功耗。这项工作提出了一套能量回收谐振脉冲触发器，利用串联电感-电容(LC)谐振来重新利用部分耗散的能量。此外，本工作还提出了使用串联LC谐振和电感调谐技术的宽带时钟结构。通过采用脉冲谐振，损耗的开关功率被回收。电感调谐技术有助于减小偏斜，提高时钟网络的稳健性。与传统的基于主次触发器的时钟网络相比，这种新的谐振式时钟架构在时钟树网络中节省了43%以上的功耗和90%的偏差，在时钟网状网络中节省了44%的功耗和90%的偏差，时钟频率范围为1-5 GHz。在标准时钟网络基准上实现了谐振时钟结构，在使用所提出的脉冲谐振触发器时，功耗降低了66%，偏差减小了6.5；而在使用谐振真单相时钟触发器时，节省了%的功率，减小了偏差12.7。
Power-performance constraints have been the key driving force that motivated the microprocessor industry to bring unique design techniques in the past two decades. The rising demand for high-performance microprocessors increases the circuit complexity and data transfer rate, resulting in higher power consumption. This work proposes a set of energy recycling resonant pulsed flip-flops to reuse some of the dissipated energy using series inductor–capacitor (LC) resonance. Moreover, this work also presents wideband clocking architectures that use series LC resonance and an inductor tuning technique. By employing pulsed resonance, the switching power dissipated is recycled back. The inductor tuning technique aids in reducing the skew, increasing the robustness of the clock networks. This new resonant clocking architecture saves over 43% power and 90% reduced skew in clock tree networks and saves 44% power and 90% reduced skew in clock mesh networks, clocking a range of 1–5 GHz frequency, compared to conventional primary–secondary flip-flop-based clock networks. Implementation of resonant clock architectures on standard clock network benchmarks depicts 66% power savings and 6.5reduced skew while using the proposed pulsed resonant flip-flop and saves 64% power and 12.7reduced skew while using the proposed resonant true single-phase clock (TSPC) flip-flop.