Total dose and Single Event Effects (SEE) in a 0.25 µm CMOS technology
Total dose and Single Event Effects (SEE) in a 0.25 µm CMOS technology
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0.25 µm CMOS 技术中的总剂量和单粒子效应 (SEE)
DOI：
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发表时间：
1998
期刊：
影响因子：
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通讯作者：
K. Kouklinas
中科院分区：
文献类型：
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作者：
G. F. Marchioro;P. Moreira;E. Noah;W. Snoeys;T. Calin;J. Cosculluela;R. Velazco;M. Nicolaidis;A. Giraldo;F. Faccio;G. Anelli;M. Campbell;M. Delmastro;P. Jarron;K. Kouklinas
个别晶体管，电阻器和移位寄存器的设计使用抗辐射布局的做法，在商业四分之一微米的过程。一个建模的努力，导致了一个令人满意的配方，用于这些布局实践中使用的封闭晶体管的有效纵横比。所有器械均接受了高达30 Mrad（SiO2）总剂量的测试。经辐照和退火处理后，NMOS和PMOS晶体管的阈值电压漂移分别为+45mV和-55mV，无漏电流，迁移率下降小于6%。电阻值增加不到10%。在W= 2 mm和L在0.36和0.64μm之间变化的晶体管上进行的噪声测量显示，NMOS的拐角噪声频率约为200 kHz，PMOS的拐角噪声频率约为12 Hz。辐射高达30 Mrad（SiO2）没有显着影响噪声性能。移位寄存器在辐照过程中以1.25MHz连续工作，并且在图案传播中没有检测到错误。未观察到功能性降解。用重离子束对移位寄存器进行辐照，研究其对单粒子效应（SEE）的敏感性。没有观察到单粒子闩锁（SEL）高达89 MeVcm 2 mg-1的LET。使用动态逻辑设计的寄存器，其阈值LET低于3.2 MeVcm 2 mg-1，被证明对单粒子翻转（SEU）比其静态逻辑对应物更敏感，其阈值LET约为15 MeVcm 2 mg-1。一种新的SEU容忍设计被证明是非常有效的存储单元。
Individual transistors, resistors and shift registers have been designed using radiation tolerant layout practices in a commercial quarter micron process. A modelling effort has led to a satisfactory formulation for the effective aspect ratio of the enclosed transistors used in these layout practices. All devices have been tested up to a total dose of 30Mrad(SiO2). The threshold voltage shift after irradiation and annealing was about +45mV for NMOS and -55mV for PMOS transistors, no leakage current appeared, and the mobility degradation was below 6%. The value of resistors increased by less than 10%. Noise measurements made on transistors with W=2mm and L varying between 0.36 and 0.64µm revealed a corner noise frequency of about 200kHz for the NMOS and 12Hz for the PMOS. Irradiation up to 30Mrad(SiO2) did not significantly affect the noise performance. The shift registers continuously operated at 1.25MHz during the irradiation, and no error was detected in the pattern propagation. No functional degradation was observed. An irradiation with a heavy ion beam was made on the shift registers to study their sensitivity to Single Event Effects (SEE). No single Event Latch-up (SEL) was observed up to a LET of 89 MeVcm2mg-1. The register designed using dynamic logic, with a threshold LET lower than 3.2 MeVcm2mg-1, proved to be considerably more sensitive to Single Event Upset (SEU) than its static logic counterpart, which had a threshold LET of about 15 MeVcm2mg-1. A novel SEU-tolerant design was demonstrated to be extremely effective as storage cell.