A 1 TB/s 1 pJ/b 6.4 ${ m mm}^{2}/{ m TB/s}$ QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM
A 1 TB/s 1 pJ/b 6.4 ${
m mm}^{2}/{
m TB/s}$ QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM
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A 1 TB/s 1 pJ/b 6.4 ${ m mm}^{2}/{ m TB/s}$ QDR 65 nm CMOS 逻辑和仿真 100 nm DRAM 之间的电感耦合接口
DOI：
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发表时间：
2012
影响因子：
4.6
通讯作者：
T. Kuroda
中科院分区：
文献类型：
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作者：
N. Miura;Mitsuko Saito;T. Kuroda
开发了65纳米互补金属氧化物半导体（CMOS）逻辑与仿真100纳米动态随机存取存储器（DRAM）之间的1 TB/s 1 pJ/b 6.4 mm2 /TB/s QDR电感耦合接口。误码率<;在1024位并行链路中检查10-10操作。与最新的有线40纳米DRAM接口相比，带宽增加到32倍，能耗和布局面积分别减少到1/8和1/22。
1 TB/s 1 pJ/b 6.4 mm2 /TB/s QDR inductive-coupling interface between 65-nm complementary metal-oxide-semicon ductor (CMOS) logic and emulated 100-nm dynamic random access memory (DRAM) is developed. BER <;10-10 operation is examined in 1024-bit parallel links. Compared to the latest wired 40-nm DRAM interface, the bandwidth is increased to 32×, and the energy consumption and the layout area are reduced to 1/8 and 1/22, respectively.