Design of a Motion Stereo VLSI Processor Based on a Transfer Bottleneck-Free Sensor/Memory Architecture
Design of a Motion Stereo VLSI Processor Based on a Transfer Bottleneck-Free Sensor/Memory Architecture
复制标题
基于无传输瓶颈传感器/存储器架构的运动立体声 VLSI 处理器的设计
DOI：
10.1541/ieejsmas.120.237
复制
发表时间：
2000
影响因子：
--
通讯作者：
M. Kameyama
中科院分区：
文献类型：
--
作者：
M. Hariyama;Seunghwan Lee;M. Kameyama
paper presents an architecture for parallel image processing that breaks the bottleneck of data transfer between an image sensor, memories and functional units. By employing an integrated image sensor, parallel data transfer between the sensor and memories can be achieved. Moreover, for parallel memory access, an optimal memory allocation is proposed that maps pixels to be accessed in parallel onto different memory modules. A functional unit allocation for local communication is also proposed to minimize the complexity of the interconnection network between memories and functional units.
