An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection
An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection
复制标题
一种使用签名寄存器进行小延迟缺陷检测的片上延迟测量技术
DOI：
10.1109/tvlsi.2011.2125994
复制
发表时间：
2012
影响因子：
2.8
通讯作者：
Hideo Ito
中科院分区：
文献类型：
--
作者：
Kentaroh Katoh;K. Namba;Hideo Ito
本文使用签名分析提出了一种延迟测量技术，并针对提出的延迟测量技术进行了扫描设计，以检测小延迟缺陷。可变的时钟生成器。拟议的扫描设计在短时间内实现了芯片延迟测量，并使用拟议的延迟测量技术和额外的锁存器来存储测试向量。与使用标准扫描设计的延迟扫描设计相比，与标准扫描设计的延迟测量相比，该面积比延迟测量架构大23.4％。平均而言，数据量为7.4％。
This paper presents a delay measurement technique using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The pro- posed measurement technique measures the delay of the explicitly sensitized paths with the resolution of the on-chip variable clock generator. The proposed scan design realizes complete on-chip delay measurement in short measurement time using the proposed delay measurement technique and extra latches for storing the test vectors. The evaluation with Rohm 0.18-μm process shows that the measurement time is 67.8% reduced compared with that of the delay measurement with standard scan design on average. The area overhead is 23.4% larger than that of the delay measurement architecture using standard scan design, and the difference of the area overhead between enhanced scan design and the proposed method is 7.4% on average. The data volume is 2.2 times of that of test set for normal testing on average.