Efficient fault simulation on many-core processors
Efficient fault simulation on many-core processors
复制标题
多核处理器上的高效故障模拟
DOI：
--
复制
发表时间：
2010
期刊：
影响因子：
--
通讯作者：
Christian G. Zoellin
中科院分区：
文献类型：
--
作者：
M. Kochte;M. Schaal;H. Wunderlich;Christian G. Zoellin
故障模拟在集成电路的测试生成、可测性设计和可靠性评估中是必不可少的。自测试结构的可靠性分析和仿真在计算上特别昂贵，因为必须评估大量的模式。在这项工作中，我们提出了一个故障模拟算法的基础上的并行模式单故障传播（PPSFP）的范例，以众核架构，并描述所涉及的算法优化。众核架构的特点是大量的简单执行单元和小的本地存储器。所提出的故障模拟算法利用这些架构的并行性，通过使用并行数据结构。该算法针对NVIDIA GT 200图形处理器（GPU）架构实现，与现有GPU故障模拟算法相比，速度提升高达17倍，与传统处理器架构上的最先进算法相比，速度提升高达16倍。
Fault simulation is essential in test generation, design for test and reliability assessment of integrated circuits. Reliability analysis and the simulation of self-test structures are particularly computationally expensive as a large number of patterns has to be evaluated. In this work, we propose to map a fault simulation algorithm based on the parallel-pattern single-fault propagation (PPSFP) paradigm to many-core architectures and describe the involved algorithmic optimizations. Many-core architectures are characterized by a high number of simple execution units with small local memory. The proposed fault simulation algorithm exploits the parallelism of these architectures by use of parallel data structures. The algorithm is implemented for the NVIDIA GT200 Graphics Processing Unit (GPU) architecture and achieves a speed-up of up to 17x compared to an existing GPU fault-simulation algorithm and up to 16x compared to state-of-the-art algorithms on conventional processor architectures.