Improving robustness of GGNMOS with P-base layer for electrostatic discharge protection in 0.5- μ m BCD process
Improving robustness of GGNMOS with P-base layer for electrostatic discharge protection in 0.5- μ m BCD process
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DOI：
10.1088/1674-1056/28/8/088501
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发表时间：
2019
影响因子：
1.7
通讯作者：
Fei 飞 Hou 侯;Ruibo 瑞博 Chen 陈;F. Du 杜;J. Liu 刘;Z. Liu 刘;Juin 俊杰 J Liou 刘
中科院分区：
文献类型：
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作者：
Fei 飞 Hou 侯;Ruibo 瑞博 Chen 陈;F. Du 杜;J. Liu 刘;Z. Liu 刘;Juin 俊杰 J Liou 刘
栅极接地 N 沟道 MOSFET (GGNMOS) 已广泛用于片上静电放电 (ESD) 保护。然而，传统GGNMOS的ESD性能因电流拥挤效应而显着降低。本文提出了一种带有 P 基极层的增强型 GGNMOS（PB-NMOS），以在不增加布局面积或附加层的情况下提高 BCD 工艺中的 ESD 鲁棒性。通过 TCAD 仿真来解释利用 P 基极层可以有效抑制所提出器件中的电流拥挤效应的根本机制。所有器件均采用 0.5 μm BCD 工艺制造，并使用传输线脉冲 (TLP) 测试仪进行测量。与传统的GGNMOS相比，所提出的PB-NMOS器件具有比传统器件更高的失效电流，可增加15.38%。此外，PB-NMOS_type3具有比传统GGNMOS低得多的触发电压，可以有效保护核心电路。
Gate-grounded N-channel MOSFET (GGNMOS) has been extensively used for on-chip electrostatic discharge (ESD) protection. However, the ESD performance of the conventional GGNMOS is significantly degraded by the current crowding effect. In this paper, an enhanced GGNMOS with P-base layer (PB-NMOS) are proposed to improve the ESD robustness in BCD process without the increase in layout area or additional layer. TCAD simulations are carried out to explain the underlying mechanisms of that utilizing the P-base layer can effectively restrain the current crowing effect in proposed devices. All devices are fabricated in a 0.5- μ m BCD process and measured using the transmission line pulsing (TLP) tester. Compared with the conventional GGNMOS, the proposed PB-NMOS devices offer a higher failure current than its conventional counterpart, which can be increased by 15.38%. Furthermore, the PB-NMOS_type3 possesses a considerably lower trigger voltage than the conventional GGNMOS to protect core circuit effectively.