VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture
VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture
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DOI：
10.1109/tcsi.2012.2221216
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发表时间：
2013-06-01
影响因子：
5.1
通讯作者：
Masera, Guido
中科院分区：
文献类型：
--
作者：
Condo, Carlo;Martina, Maurizio;Masera, Guido
灵活的、可重构的体系结构在通信领域得到了广泛的欢迎。特别是，物理层的可重构体系结构是一种有吸引力的解决方案，不仅可以在不同的编码模式之间切换，还可以实现互操作性。本文致力于设计一种可重构的Turbo码和LDPC码译码结构。本文的创新之处在于：i)解决了重构问题，引入了一种形式化和系统化的处理方法，据我们所知，这是以前没有解决过的问题；ii)提出了一种基于NoC的可重构Turbo/LDPC译码结构，并证明了该结构可以以较小的复杂度开销获得广泛的灵活性。得到的结果表明，在不暂停解码活动的情况下，可以在大多数考虑的通信标准之间进行动态切换。此外，版图后的结果显示，在最坏的情况下，根据WiMAX标准定制所提出的架构将导致2.75mM(2)的面积占用和101.5 mW的功耗。
Flexible and reconfigurable architectures have gained wide popularity in the communications field. In particular, reconfigurable architectures for the physical layer are an attractive solution not only to switch among different coding modes but also to achieve interoperability. This work concentrates on the design of a reconfigurable architecture for both turbo and LDPC codes decoding. The novel contributions of this paper are: i) tackling the reconfiguration issue introducing a formal and systematic treatment that, to the best of our knowledge, was not previously addressed and ii) proposing a reconfigurable NoC-based turbo/LDPC decoder architecture and showing that wide flexibility can be achieved with a small complexity overhead. Obtained results show that dynamic switching between most of considered communication standards is possible without pausing the decoding activity. Moreover, post-layout results show that tailoring the proposed architecture to the WiMAX standard leads to an area occupation of 2.75 mm(2) and a power consumption of 101.5 mW in the worst case.