The Potential of Dynamic Binary Modification and CPU-FPGA SoCs for Simulation
The Potential of Dynamic Binary Modification and CPU-FPGA SoCs for Simulation
复制标题
动态二进制修改和 CPU-FPGA SoC 用于仿真的潜力
DOI：
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发表时间：
2017
期刊：
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通讯作者：
M. Luján
中科院分区：
文献类型：
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作者：
John Mawer;Oscar Palomar;Cosmin Gorgovan;A. Nisbet;W. Toms;M. Luján
在本文中，我们描述了一个灵活的基础设施，可以直接接口未修改的应用程序可执行程序与FPGA硬件加速IP，以1），促进更快的计算机架构仿真，2），原型微架构或加速器IP。动态二进制修改工具插件通过用户空间硬件控制库提供的灵活软件接口直接连接到评估中的应用程序，该硬件控制库还管理对参数化Bluespec IP库的访问。我们展示了我们的基础设施的潜力与未修改的应用程序可执行文件的两个用例，1），一个可执行文件被动态检测，以生成加载/存储和程序计数器事件，发送到FPGA硬件加速的有序微架构流水线，和内存层次结构模型，和2），一个分支预测器的设计原型使用FPGA。我们的基础设施的关键功能是能够在指令级粒度进行仪器化，在用户级专门编码，并在运行时动态发现和使用可用的硬件模型，因此，我们使软件开发人员能够快速调查和评估参数化的Bluespec微架构和加速器IP模型。我们将我们的系统与行业标准的ARM架构模拟器GEM 5进行了比较，以证明准确性和相对性能，即使我们的系统在Xilinx Zynq 7000 FPGA板上实现，FPGA和ARM Cortex A9处理器紧密耦合，它的性能也优于在Xeon上运行的GEM 5，内存为32 GB（比本机执行慢400倍vs 700倍）。
In this paper we describe a flexible infrastructure that can directly interface unmodified application executables with FPGA hardware acceleration IP in order to 1), facilitate faster computer architecture simulation, and 2), to prototype microarchitecture or accelerator IP. Dynamic binary modification tool plugins are directly interfaced to the application under evaluation via flexible software interfaces provided by a userspace hardware control library that also manages access to a parameterised Bluespec IP library. We demonstrate the potential of our infrastructure with two use cases with unmodified application executables where, 1), an executable is dynamically instrumented to generate load/store and program counter events that are sent to FPGA hardware accelerated in-order microarchitecture pipeline, and memory hierarchy models, and 2), the design of a branch predictor is prototyped using an FPGA. The key features of our infrastructure are the ability to instrument at instruction level granularity, to code exclusively at the user level, and to dynamically discover and use available hardware models at run time, thus, we enable software developers to rapidly investigate and evaluate parameterised Bluespec microarchitecture and accelerator IP models. We present a comparison between our system and GEM5, the industry standard ARM architecture simulator, to demonstrate accuracy and relative performance, even though our system is implemented on an Xilinx Zynq 7000 FPGA board with tightly coupled FPGA and ARM Cortex A9 processors, it outperforms GEM5 running on a Xeon with 32GBs of RAM (400x vs 700x slowdown over native execution).