On Microarchitectural Mechanisms for Cache Wearout Reduction
On Microarchitectural Mechanisms for Cache Wearout Reduction
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DOI：
10.1109/tvlsi.2016.2625809
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发表时间：
2017-03
影响因子：
2.8
通讯作者：
A. Valero;Negar Miralaei;S. Petit;J. Sahuquillo;Timothy M. Jones
中科院分区：
文献类型：
--
作者：
A. Valero;Negar Miralaei;S. Petit;J. Sahuquillo;Timothy M. Jones
热载体注入（HCI）和偏置温度不稳定性（BTI）是在微处理器的寿命中增加晶体管阈值的主要效果当晶体管从逻辑“ 0”转换为“ 1”，反之亦然时，BTI是晶体管在长时间内保持相同的逻辑值的结果。经常访问的第一级（L1）缓存的SRAM细胞，因此它们对性能至关重要，并且它们不断衰老。在L1数据缓存中。根据这些观察结果，在缓存中的书面值在大量的时间内识别给定的逻辑值。逻辑“ 0”值通过关闭特定的数据字节来存储在单元格中。
Hot carrier injection (HCI) and bias temperature instability (BTI) are two of the main deleterious effects that increase a transistor’s threshold voltage over the lifetime of a microprocessor. This voltage degradation causes slower transistor switching and eventually can result in faulty operation. HCI manifests itself when transistors switch from logic “0” to “1” and vice versa, whereas BTI is the result of a transistor maintaining the same logic value for an extended period of time. These failure mechanisms are especially acute in those transistors used to implement the SRAM cells of first-level (L1) caches, which are frequently accessed, so they are critical to performance, and they are continuously aging. This paper focuses on microarchitectural solutions to reduce transistor aging effects induced by both HCI and BTI in the data array of L1 data caches. First, we show that the majority of cell flips are concentrated in a small number of specific bits within each data word. In addition, we also build upon the previous studies, showing that logic “0” is the most frequently written value in a cache by identifying which cells hold a given logic value for a significant amount of time. Based on these observations, this paper introduces a number of architectural techniques that spread the number of flips evenly across memory cells and reduce the amount of time that logic “0” values are stored in the cells by switching OFF specific data bytes. Experimental results show that the threshold voltage degradation savings range from 21.8% to 44.3% depending on the application.