Speculative sequential consistency with little custom storage
Speculative sequential consistency with little custom storage
复制标题
推测顺序一致性，几乎没有自定义存储
DOI：
10.1109/pact.2002.1106016
复制
发表时间：
2002
期刊：
影响因子：
--
通讯作者：
B. Falsafi
中科院分区：
文献类型：
--
作者：
C. Gniady;B. Falsafi
本文提出了SC++lite，一个顺序一致的系统，放宽内存顺序推测性弥合内存一致性模型之间的性能差距。推测性地放松存储器顺序的先前提议需要大的定制片上存储装置以在放松存储器顺序时维持推测性处理器和存储器状态的历史。SC++lite使用内存层次结构来存储推测历史，为推测SC系统提供了一个可扩展的路径，跨广泛的应用程序和系统延迟。我们使用共享内存多处理器的周期精确模拟表明，SC++lite可以完全放松内存顺序，同时几乎消除了自定义片上存储的需要。此外，虽然对存储的需求随着更大的内存延迟而显着增加，但SC++lite放松内存顺序的能力对内存延迟仍然不敏感。SC++lite系统可以将基本SC系统的性能提高28%，而在具有16个处理器的系统中只有2 KB的自定义存储。相比之下，具有自定义存储的推测性SC系统需要51 KB的存储来将性能提高31%。
This paper proposes SC++lite, a sequentially consistent system that relaxes memory order speculatively to bridge the performance gap among memory consistency models. Prior proposals to speculatively relax memory order require large custom on-chip storage to maintain a history of speculative processor and memory state while memory order is relaxed. SC++lite uses the memory hierarchy to store the speculative history, providing a scalable path for speculative SC systems across a wide range of applications and system latencies. We use cycle-accurate simulation of shared-memory multiprocessors to show that SC++lite can fully relax memory order while virtually obviating the need for custom on-chip storage. Moreover while demand for storage increases significantly with larger memory latencies, SC++lite's ability to relax memory order remains insensitive to memory latency. An SC++lite system can improve performance over a base SC system by 28% with only 2 KB of custom storage in a system with 16 processors. In contrast, speculative SC systems with custom storage require 51 KB of storage to improve performance by 31% over a base SC system.