Boosting chipkill capability under retention-error induced reliability emergency
Boosting chipkill capability under retention-error induced reliability emergency
复制标题
提高保留错误引起的可靠性紧急情况下的芯片消除能力
DOI：
10.1145/3287624.3287639
复制
发表时间：
2019
期刊：
影响因子：
--
通讯作者：
Yang, Jun
中科院分区：
文献类型：
--
作者：
Zhang, Xianwei;Wang, Rujia;Zhang, Youtao;Yang, Jun
高嵌入式系统的基于DRAM的主存储器面临两个设计挑战：（i）降低可靠性;以及（ii）增加功率和能量消耗。虽然可以分别采用chipkill ECC（纠错码）和多速率刷新来解决它们，但是两者的简单集成导致3倍或更多的SDC（静默数据损坏）错误，并且不能满足系统可靠性保证。在本文中，我们提出了PlusN，一个硬件辅助的内存错误保护设计，自适应地提高基线芯片的能力，以解决可靠性紧急情况。基于运行时的错误概率评估，系统在基线chipkill和PlusN之间切换其内存保护--后者生成更强的ECC，存储和访问开销较低。实验结果表明，PlusN在不同的可靠性紧急情况下都能有效地保证系统的可靠性。
The DRAM based main memory of high embedded systems faces two design challenges: (i) degrading reliability; and (ii) increasing power and energy consumption. While chipkill ECC (error correction code) and multi-rate refresh may be adopted to address them, respectively, a simple integration of the two results in 3x or more SDC (silent data corruption) errors and failing to meet the system reliability guarantee. This is referred to asreliability emergency.In this paper, we propose PlusN, a hardware-assisted memory error protection design that adaptively boosts the baseline chipkill capability to address the reliability emergency. Based on the error probability assessment at runtime, the system switches its memory protection between the baseline chipkill and PlusN --- the latter generates a stronger ECC with low storage and access overheads. Our experimental results show that PlusN can effectively enforce the system reliability guarantee under different reliability emergency scenarios.