Pulse-Width Modulation based Dot-Product Engine for Neuromorphic Computing System using Memristor Crossbar Array
Pulse-Width Modulation based Dot-Product Engine for Neuromorphic Computing System using Memristor Crossbar Array
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DOI：
10.1109/iscas.2018.8351276
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发表时间：
2018-05
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通讯作者：
Hao Jiang;K. Yamada;Z. Ren;T. Kwok;Fu Luo;Qing Yang;Xiaorong Zhang;J. Yang;Qiangfei Xia;Yiran Chen;Hai Helen Li;Qing Wu;Mark D. Barnell
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文献类型：
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作者：
Hao Jiang;K. Yamada;Z. Ren;T. Kwok;Fu Luo;Qing Yang;Xiaorong Zhang;J. Yang;Qiangfei Xia;Yiran Chen;Hai Helen Li;Qing Wu;Mark D. Barnell
点积引擎（DPE）是在硬件中实现神经网络的关键电路。最近发展起来的忆阻器交叉杆阵列技术，能够有效地执行点积乘法并真实的实时更新其权重，已被认为是构建高效神经网络计算系统的可行技术之一。本文提出并分析了基于脉宽调制（PWM）的数字脉冲处理器。这里，基于PWM的信号而不是传统的幅度调制（AM）信号被用作计算变量。与现有的基于AM的系统相比，这种PWM对应物提供了一种替代方法，以降低其外围电路的功耗和芯片面积。当阵列的大小和/或数量增加时，功率和面积节省变得更加突出。这种新方法还提供了迫切需要的可扩展性，以适应更高精度的计算变量。在本文中，一个4位（可以很容易地扩展到8位）前馈神经网络与3位的权重（忆阻器的电导）构建使用建议的PWM DPE识别数字从MNIST数据集。电路系统采用130 nm标准CMOS工艺实现。整个电路系统功耗约为53 mW，平均识别准确率超过86%。
The Dot-Product Engine (DPE) is a critical circuit for implementing neural networks in hardware. The recent-developed memristor crossbar array technology, which is able to efficiently carry out dot-product multiplication and update its weights in real time, has been considered as one of the viable technologies to build a high-efficient neural network computing system. In this paper, the Pulse-Width-Modulation (PWM) based DPE has been presented and analyzed. Here, the PWM based signal, instead of the traditional amplitude modulated (AM) signal, is used as the computation variable. Comparing to the existing AM based system, this PWM counterpart provides an alternative approach to reduce the power consumption and chip area of its peripheral circuits. Power and area saving becomes more prominent when the size and/or the number of arrays increase. This new approach also provides the critically needed scalability to accommodate the computation variable with higher precision. In this paper, a 4-bit (can be easily expanded to 8-bit) feed forward neural network with 3-bit weights (memristor's conductance) is constructed using the proposed PWM DPE to identify digits from the MNIST data set. The circuit system is implemented in 130 nm standard CMOS technology. The entire circuit system consumes about 53mW with more than 86% recognition accuracy in average.