Robust asymmetric 6T-SRAM cell for low-power operation in nano-CMOS technologies
Robust asymmetric 6T-SRAM cell for low-power operation in nano-CMOS technologies
复制标题
稳健的非对称 6T-SRAM 单元，适用于纳米 CMOS 技术中的低功耗运行
DOI：
10.1049/el.2010.2817
复制
发表时间：
2010
影响因子：
1.1
通讯作者：
Azam T
中科院分区：
文献类型：
--
作者：
Azam T
An asymmetric 6T-SRAM cell design is presented for reliable low-power circuit operation under large variability. A low overhead write assist circuit is added to increase the write-noise-margin (WNM) and improve the write speed/power. Sizing is used to strengthen the pull-down transistor of the feedback inverter of the single ended read circuit to enhance the static-noise-margin (SNM). Monte Carlo simulations indicate a 90% improvement in SNM and a boost in the WNM of 108% compared to the conventional 6T-SRAM design. Comparative analysis of a 65nm 64×32 bit SRAM designed using both SRAM cells (Symmetric-6T and Asymmetric-6T) shows the write delay and power decrease by 46% and 35%, respectively, while total power decreases by 52% using the proposed design.
适用于超低电压应用的单端 6T SRAM 单元设计
影响因子：
0.8
作者：
Jawar Singh;D. Pradhan;S. Hollis;S. Mohanty
通讯作者：
S. Mohanty