A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation- Register Analog-to-Digital Converter With Digital Calibration
A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation- Register Analog-to-Digital Converter With Digital Calibration
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DOI：
10.1109/jssc.2011.2163556
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发表时间：
2011-11-01
影响因子：
5.4
通讯作者：
Chiu, Yun
中科院分区：
文献类型：
--
作者：
Liu, Wenbo;Huang, Pingli;Chiu, Yun
为了提高开关电容逐次逼近寄存器(SAR)模数转换器(ADC)的性能，提出了一种亚基2冗余结构。这种冗余不仅保证了转换器的静态非线性是数字可纠正的，而且还提供了对抗转换过程中的动态误差的手段，从而加快了SAR架构的速度。文中还描述了一种基于扰动的数字校准技术，该技术与体系结构选择紧密结合，可同时识别ADC的多个电容失配误差，从而能够缩小所有采样电容的尺寸，以节省功耗和硅面积。一个12位原型在22.5MS/S下测试了奈奎斯特70.1dB信噪加失真比(SNDR)和90.3dBNyquist无杂散动态范围(SFDR)，同时在1.2V电源中消耗3.0 mW功率，在0.13微米工艺中占用0.06 mm(2)硅面积。该模数转换器的品质因数(FOM)在22.5MS/S和45MS/S时分别为51.3FJ/STEP和36.7FJ/STEP。
This paper presents a sub-radix-2 redundant architecture to improve the performance of switched-capacitor successive-approximation-register (SAR) analog-to-digital converters (ADCs). The redundancy not only guarantees digitally correctable static nonlinearities of the converter, it also offers means to combat dynamic errors in the conversion process, and thus, accelerating the speed of the SAR architecture. A perturbation-based digital calibration technique is also described that closely couples with the architecture choice to accomplish simultaneous identification of multiple capacitor mismatch errors of the ADC, enabling the downsizing of all sampling capacitors to save power and silicon area. A 12-bit prototype measured a Nyquist 70.1-dB signal-to-noise-plus-distortion ratio (SNDR) and a Nyquist 90.3-dB spurious free dynamic range (SFDR) at 22.5 MS/s, while dissipating 3.0-mW power from a 1.2-V supply and occupying 0.06-mm(2) silicon area in a 0.13-mu m CMOS process. The figure of merit (FoM) of this ADC is 51.3 fJ/step measured at 22.5 MS/s and 36.7 fJ/step at 45 MS/s.