A 14-bit 2.5-GS/s DAC using CAL-TRZ
A 14-bit 2.5-GS/s DAC using CAL-TRZ
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DOI：
10.1109/mocast.2016.7495116
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发表时间：
2016-05
期刊：
影响因子：
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通讯作者：
Guoting Wu;Qi Wei;Xiayang Chen;F. Qiao
中科院分区：
文献类型：
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作者：
Guoting Wu;Qi Wei;Xiayang Chen;F. Qiao
采用55 nm CMOS工艺设计了一个14位2.5 GS/s电流舵数模转换器（DAC）。对于如此高的采样率，时间松弛交织数字随机归零（TRI-DRRZ）是一种有效的方法，通过随机化开关毛刺来提高DAC的动态性能。本文提出了一种称为CAL-TRZ的实用技术。它将TRI-DRRZ与数字校准操作相结合。数字校准用于确保DAC的静态线性度，并进一步提高小尺寸电流源晶体管的动态性能。预布局仿真结果表明，该DAC在1250 MHz奈奎斯特带宽内实现了>78 dB的无杂散动态范围（SFDR），最高有效位（MSB）电流源的失配预设为0.5%。
A 14-bit 2.5-GS/s current-steering digital-to-analog converter (DAC) was designed in a 55-nm CMOS technology. For such a high sampling rate, time-relaxed interleaving digital random return-to-zero (TRI-DRRZ) is an effective method to improve the dynamic performance of the DAC by randomizing the switch glitches. A useful technique called CAL-TRZ is proposed in this paper. It combines TRI-DRRZ with a digital calibration operation. The digital calibration is used to ensure the static linearity of the DAC and further improve dynamic performance with small-size current source transistors. The pre-layout simulation shows that the proposed DAC achieves a spurious-free dynamic range (SFDR) >78 dB over 1250 MHz Nyquist bandwidth with a preset 0.5% mismatch of most significant bits (MSB) current sources.