Prevention of Oscillatory False Triggering of GaN-FETs by Balancing Gate-Drain Capacitance and Common-Source Inductance
Prevention of Oscillatory False Triggering of GaN-FETs by Balancing Gate-Drain Capacitance and Common-Source Inductance
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DOI：
10.1109/tia.2018.2868272
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发表时间：
2019
影响因子：
4.4
通讯作者：
K. Umetani;Ryunosuke Matsumoto;E. Hiraki
中科院分区：
文献类型：
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作者：
K. Umetani;Ryunosuke Matsumoto;E. Hiraki
氮化镓场效应晶体管（GaN-FET）是具有快速开关能力的有前途的开关器件。然而，它们通常具有低的栅极阈值电压，遭受对错误触发的敏感性。特别地，振荡错误触发，即，在快速切换之后可能发生自持重复错误触发，这对于工业应用是严重的障碍。本文旨在阐明防止这种现象的设计指导。已知振荡误触发是由GaN-FET形成的寄生振荡器电路、其寄生电容和布线的寄生电感引起的。本文分析了该振子的非振荡条件。结果表明，合理的栅漏电容与共源电感之比是防止振荡误触发的关键。实验成功地验证了这一分析结果，支持适当的设计，以防止振荡误触发的有效性。
Gallium-nitride-field-effect transistors (GaN-FETs) are promising switching devices with fast switching capability. However, they commonly have low gate threshold voltage, suffering from susceptibility to the false triggering. Particularly, the oscillatory false triggering, i.e., a self-sustaining repetitive false triggering, can occur after a fast switching, which is a severe obstacle for industrial applications. The purpose of this paper is to elucidate the design instruction for preventing this phenomenon. The oscillatory false triggering is known to be caused by the parasitic oscillator circuit formed of a GaN-FET, its parasitic capacitance and the parasitic inductance of the wiring. This paper analyzed the nonoscillatory condition of this oscillator. The result revealed an appropriate ratio between the gate-drain capacitance and the common-source inductance is a key to prevent the oscillatory false triggering. Experiment successfully verified this analysis result, supporting the effectiveness of the appropriate design of this ratio for preventing the oscillatory false triggering.