Strategies for achieving improved processor throughput
Strategies for achieving improved processor throughput
复制标题
提高处理器吞吐量的策略
DOI：
10.1145/115952.115988
复制
发表时间：
1991
期刊：
影响因子：
--
通讯作者：
A. Pleszkun
中科院分区：
文献类型：
--
作者：
M. Farrens;A. Pleszkun
由于指令之间的相关性，深度流水线处理器的发行率相对较低。在这篇文章中，我们研究了将第二个指令流交织到流水线中的可能性，该流水线将在第一个流无法执行的周期内发出指令。这种交织有可能显著增加处理器的吞吐量，而不会严重影响任一进程的执行。我们提出了一种最多2个指令流的动态交织，它们共享机器的流水线功能单元。为了支持2个指令流的交织，有许多交织策略。对其进行了描述和讨论。最后，通过模拟几种机器变量的交织策略，对处理器吞吐量的提高程度进行了评估。
Deeply pipelined processors have relatively low issue rates due to dependencies between instructions. In this paper we examine the possibility of interleaving a second stream of instructions into the pipeline, which would issue instructions during the cycles the first stream was unable to. Such an interleaving has the potential to significantly increase the throughput of a processor without seriously imparing the execution of either process. We propose a dynamic interleaving of at most 2 instructions streams, which share the the pipelined functional units of a machine. To support the interleaving of 2 instruction streams a number of interleaving policies are. described and discused. Finally, the amount of improvement in processor throughput is evaluated by simulating the interleaving policies for several machine varianv;.