Low-Latency Adiabatic Quantum-Flux-Parametron Circuit Integrated With a Hybrid Serializer/Deserializer
Low-Latency Adiabatic Quantum-Flux-Parametron Circuit Integrated With a Hybrid Serializer/Deserializer
复制标题
与混合串行器/解串器集成的低延迟绝热量子通量参量管电路
DOI：
10.1109/access.2022.3230447
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发表时间：
2022
期刊：
影响因子：
3.9
通讯作者：
Takeuchi Naoki
中科院分区：
文献类型：
--
作者：
Hironaka Yuki;Yamae Taiki;Ayala Christopher L.;Yoshikawa Nobuyuki;Takeuchi Naoki
绝热量子流参变（AQFP）逻辑是一种超低功耗超导逻辑家族。AQFP逻辑门由专用时钟方案供电和时钟控制，该方案使用交流激励电流实现节能切换过程（绝热切换）。我们提出了一种低延迟时钟方案，延迟线时钟，并演示了基本的AQFP逻辑门。为了测试更复杂的电路，串行器/串行器（SerDes）应该被合并到被测AQFP电路中，因为输入/输出（I/O）电缆的数量受到设备的限制。因此，在本研究中，我们提出并开发了一种新的SerDes测试延迟线时钟AQFP电路相结合的AQFP和快速单通量量子（RSFQ）的逻辑家庭，我们称之为AQFP/RSFQ混合SerDes。混合SerDes包括RSFQ移位寄存器，以便于串并和并串转换期间的数据存储。此外，混合SerDes中的所有组件电路都由相同的激励电流进行时钟控制，以同步AQFP和RSFQ部分。我们制造和演示了一个延迟线时钟AQFP电路（8至3编码器，这是有史以来设计的最大的延迟线时钟电路）集成的混合SerDes在4.2 K高达4.5 GHz。我们的测量结果表明，混合SerDes使延迟线时钟AQFP电路的测试只有几个I/O电缆，因此是一个强大的工具，非常大规模集成AQFP电路的发展。
Adiabatic quantum-flux-parametron (AQFP) logic is an ultra-low-power superconductor logic family. AQFP logic gates are powered and clocked by dedicated clocking schemes using ac excitation currents to implement an energy-efficient switching process, adiabatic switching. We have proposed a low-latency clocking scheme, delay-line clocking, and demonstrated basic AQFP logic gates. In order to test more complex circuits, a serializer/deserializer (SerDes) should be incorporated into the AQFP circuit under test, since the number of input/output (I/O) cables is limited by equipment. Therefore, in the present study we propose and develop a novel SerDes for testing delay-line-clocked AQFP circuits by combining AQFP and rapid single-flux-quantum (RSFQ) logic families, which we refer to as the AQFP/RSFQ hybrid SerDes. The hybrid SerDes comprises RSFQ shift registers to facilitate the data storage during serial-to-parallel and parallel-to-serial conversion. Furthermore, all the component circuits in the hybrid SerDes are clocked by the identical excitation current to synchronize the AQFP and RSFQ parts. We fabricate and demonstrate a delay-line-clocked AQFP circuit (8-to-3 encoder, which is the largest delay-line-clocked circuit ever designed) integrated with the hybrid SerDes at 4.2 K up to 4.5 GHz. Our measurement results indicate that the hybrid SerDes enables the testing of delay-line-clocked AQFP circuits with only a few I/O cables and is thus a powerful tool for the development of very large-scale integration AQFP circuits.