A CMOS Instrumentation Amplifier With 90-dB CMRR at 2-MHz Using Capacitive Neutralization: Analysis, Design Considerations, and Implementation
A CMOS Instrumentation Amplifier With 90-dB CMRR at 2-MHz Using Capacitive Neutralization: Analysis, Design Considerations, and Implementation
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使用电容中和在 2MHz 下具有 90dB CMRR 的 CMOS 仪表放大器：分析、设计考虑因素和实现
DOI：
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
Xiao Liu
中科院分区：
文献类型：
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作者：
A. Worapishet;A. Demosthenous;Xiao Liu
在仪表放大器（IA）设计中使用“电流反馈”的好处是众所周知的。在本文中，我们分析了失配机制，随机和系统的类型，影响共模抑制比（CMRR）的本地电流反馈IA拓扑结构的性能。我们推导出的共模增益频率响应的解析表达式，由于随机失配（漏极，漏极-源极电导和寄生电容），并通过仿真验证分析的完整性。为了解决系统的输入对晶体管的漏极电容的失配，我们采用电容中和，并验证其有效性，在实践中从制造IA芯片样品在0.35- CMOS工艺技术。在2 MHz（3 dB带宽）下，采用我们的中和技术制造的20个样品的实测平均共模增益改善约为20 dB。当考虑差分增益响应（33.7 dB）时，中和IA在2 MHz时的平均CMRR超过90 dB。IA占用面积为0.068，功耗为0.85 mW，采用3 V电源供电。该电路预期用于宽带生物阻抗谱应用。
The benefits of using “current feedback” in instrumentation amplifier (IA) design are well known. In this paper, we analyze the mismatch mechanisms, both random and systematic types, which influence the common-mode rejection ratio (CMRR) performance of the local current feedback IA topology. We derive analytical expressions for the common-mode gain frequency response due to random mismatches (transconductance, drain-source conductance and parasitic capacitance) and verify the integrity of the analysis through simulation. To address the systematic mismatch in the drain capacitance of the input pair transistors, we employ capacitive neutralization and verify its effectiveness in practice from the fabricated IA chip samples in a 0.35- CMOS process technology. The measured average common-mode gain improvement for the 20 fabricated samples employing our neutralization technique is about 20 dB at 2 MHz ( 3 dB bandwidth). When taking into account the differential gain response (33.7 dB), the average CMRR of the neutralized IA at 2 MHz exceeds 90 dB. The IA occupies an area of 0.068 and dissipates 0.85 mW from a 3-V power supply. The circuit is intended for a wideband bioimpedance spectroscopy application.