A comparative analysis of front-end and back-end compatible silicon photonic on-chip interconnects

A comparative analysis of front-end and back-end compatible silicon photonic on-chip interconnects
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前端和后端兼容硅光子片上互连的比较分析

DOI:
10.1145/2947357.2947362
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发表时间:
2016
期刊:
2016 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)
影响因子:
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通讯作者:
S. Pasricha
S. Pasricha
中科院分区:
--
文献类型:
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作者:
Ishan G. Thakkar;Sai Vineel Reddy Chittamuru;S. Pasricha

文献摘要

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相似文献

采用后端兼容硅光子(BCSP)材料制作的光子器件可以独立于复杂的CMOS前端兼容硅光子(FCSP)工艺,显著提高光子片上网络(PNoC)架构的性能。在本文中,我们提出了一个详细的比较分析的CMOS前端和后端兼容的硅光子互连器件的设计权衡。通过对多个器件级和链路级设计参数进行跨层优化,实现了基于BCSP器件的高能效片上光子互连设计。尽管BCSP器件的光电性能较差,但BCSP片上链路的优化设计比FCSP片上链路具有更高的能效和总带宽。我们的实验分析比较了使用BCSP和FCSP链路的架构级别,并表明,基于BCSP的Firefly PNoC的优化设计实现了1.15倍的吞吐量和12.4%的能量,平均比基于FCSP的Firefly PNoC的优化设计。同样,基于BCSP的Corona PNoC的优化设计实现了比基于FCSP的Corona PNoC的优化设计高3.5倍的吞吐量和平均低39.5%的每比特能量。
Photonic devices fabricated with back-end compatible silicon pho-tonic (BCSP) materials can provide independence from the complex CMOS front-end compatible silicon photonic (FCSP) process, to sig-nificantly enhance photonic network-on-chip (PNoC) architecture performance. In this paper, we present a detailed comparative analy-sis of a number of design tradeoffs for CMOS front-end and back-end compatible devices for silicon photonic interconnects. A cross-layer optimization of multiple device-level and link-level design pa-rameters is performed to enable the design of energy-efficient on-chip photonic interconnects using BCSP devices. The optimized design of BCSP on-chip links renders more energy-efficiency and aggregate bandwidth than FCSP on-chip links, in spite of the inferior opto-elec-tronic properties of BCSP devices. Our experimental analysis com-pares the use of BCSP and FCSP links at the architecture level, and shows that the optimized design of the BCSP-based Firefly PNoC achieves 1.15x greater throughput and 12.4% less energy-per-bit on average than the optimized design of FCSP-based Firefly PNoC. Similarly, the optimized design of the BCSP-based Corona PNoC achieves 3.5x greater throughput and 39.5% less energy-per-bit on average than the optimized design of FCSP-based Corona PNoC.