RETROSPECTIVE: High Performance Cache Replacement Using Re-Reference Interval Prediction (RRIP)
RETROSPECTIVE: High Performance Cache Replacement Using Re-Reference Interval Prediction (RRIP)
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发表时间：
2023
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通讯作者：
A. Jaleel;‡. KevinB.Theobald;§. SimonC.SteelyJr;J. Emer;†. Nvidia;§. OregonPERS
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作者：
A. Jaleel;‡. KevinB.Theobald;§. SimonC.SteelyJr;J. Emer;†. Nvidia;§. OregonPERS
在这篇ISCA 2010论文发表时，片上末级缓存（LLC）大小和多核处理器的不断增长使缓存管理重新成为工业界和学术界的热门研究课题。这项工作是英特尔产品和研究团队之间的合作。英特尔当时遵循其“滴答”模式，交替架构重新设计与过程收缩，产品团队总是寻求新的功能，以提供足够的性能增益每个版本。Kevin Theobald是英特尔俄勒冈州设计团队的性能架构师，而Aamer Jaleel、Simon Steely和Joel Emer则是英特尔VSSAD高级研发团队的成员。两个团队都在独立地寻找提高LLC业绩的方法。这项工作是他们共同努力的结果，以更低的成本超过了LRU。该设计进入Ivy Bridge [1]和后来的处理器，并从此影响了缓存研究和行业范围的缓存设计。
At the time of this ISCA 2010 paper, growing on-chip lastlevel cache (LLC) sizes and multi-core processors had revived cache management as a hot research topic in industry and academia. This work was a collaboration between Intel’s product and research teams. Intel was then following its “tick-tock” paradigm, alternating architecture re-designs with process shrinks, and product teams always sought new features to give adequate performance gains per release. Kevin Theobald was a Performance Architect on Intel’s Oregon design team while Aamer Jaleel, Simon Steely, and Joel Emer were part of Intel’s VSSAD, an advanced R&D group. Both teams were independently seeking ways to improve LLC performance. This work is the result of combining their efforts that outperformed LRU at a lower cost. The design went into Ivy Bridge [1] and later processors, and has since influenced cache research and industry-wide cache designs.