DEC-NoC: An Approximate Framework Based on Dynamic Error Control with Applications to Energy-Efficient NoCs
DEC-NoC: An Approximate Framework Based on Dynamic Error Control with Applications to Energy-Efficient NoCs
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DOI：
10.1109/iccd.2018.00078
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发表时间：
2018-10
期刊：
影响因子：
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通讯作者：
Yuechen Chen;Md Farhadur Reza;A. Louri
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文献类型：
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作者：
Yuechen Chen;Md Farhadur Reza;A. Louri
网络上的网络（NOC）已成为用于多个核心系统和芯片系统的标准片上通信面料。但是，随着芯片芯的数量增加，功率消耗也会增加。最近的研究表明，NOC功耗可达到总体芯片功率的40％[1] - [3]。已经部署了大量的研究工作，以显着降低NOC功耗。在本文中，我们以近似计算技术为基础，并提出了一种称为DEC-NOC的近似通信方法，用于减少NOC功耗。所提出的DEC-NOC利用应用程序的误差容忍度并动态减少数据包传输中的错误检查和校正量，从而大大减少了转载数据包的数量。数据包重传的减少导致功耗降低。我们使用PARSEC基准套件的循环精确模拟表明，与具有常规误差控制技术的NOC架构相比，DEC-NOC可实现多达56％的延迟降低和高达58％的动态功率
Network-on-Chips (NoCs) have emerged as the standard on-chip communication fabrics for multi/many core systems and system on chips. However, as the number of cores on chip increases, so does power consumption. Recent studies have shown that NoC power consumption can reach up to 40% of the overall chip power [1]-[3]. Considerable research efforts have been deployed to significantly reduce NoC power consumption. In this paper, we build on approximate computing techniques and propose an approximate communication methodology called DEC-NoC for reducing NoC power consumption. The proposed DEC-NoC leverages applications' error tolerance and dynamically reduces the amount of error checking and correction in packet transmission, which results in a significant reduction in the number of retransmitted packets. The reduction in packet retransmission results in reduced power consumption. Our cycle accurate simulation using PARSEC benchmark suites shows that DEC-NoC achieves up to 56% latency reduction and up to 58% dynamic power reduction compared to NoC architectures with conventional error control techniques