A VLSI architecture for high-performance, low-cost, on-chip learning
A VLSI architecture for high-performance, low-cost, on-chip learning
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用于高性能、低成本片上学习的 VLSI 架构
DOI：
10.1109/ijcnn.1990.137621
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发表时间：
1990
期刊：
影响因子：
--
通讯作者：
D. Hammerstrom
中科院分区：
文献类型：
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作者：
D. Hammerstrom
所描述的X1体系结构的动机是开发适合解决大型现实问题的廉价商业硬件。这样的架构必须是面向系统的，并且足够灵活，能够执行任何神经网络算法，并与现有的硬件和软件协同工作。神经网络的早期应用必须与现有的硬件和软件技术相结合。使用最先进的技术和创新的体系结构技术，作者的体系结构接近模拟系统的速度和成本，同时保留了大型通用并行机器的大部分灵活性。作者针对一组特定的应用程序，并相应地进行了成本-性能权衡。目标是一种架构，可以被认为是神经计算的通用微处理器
The motivation for the X1 architecture described was to develop inexpensive commercial hardware suitable for solving large, real-world problems. Such an architecture must be systems oriented and flexible enough to execute any neural network algorithm and work cooperatively with existing hardware and software. The early application of neural networks must proceed in conjunction with existing technologies, both hardware and software. Using state-of-the-art technology and innovative architectural techniques, the author's architecture approaches the speed and cost of analog systems while retaining much of the flexibility of large, general-purpose parallel machines. The author has aimed at a particular set of applications and has made cost-performance tradeoffs accordingly. The goal is an architecture that could be considered a general-purpose microprocessor for neurocomputing