Throttling Control for Bufferless Routing in On-chip Networks
Throttling Control for Bufferless Routing in On-chip Networks
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DOI：
10.1109/mcsoc.2012.25
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发表时间：
2012-09
期刊：
影响因子：
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通讯作者：
Yicheng Guan;Cisse Ahmadou Dit Adi;T. Miyoshi;M. Koibuchi;H. Irie;T. Yoshinaga
中科院分区：
文献类型：
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作者：
Yicheng Guan;Cisse Ahmadou Dit Adi;T. Miyoshi;M. Koibuchi;H. Irie;T. Yoshinaga
随着单个芯片上的核心集成数量的增加，缓冲器消耗了大量的能量，并占用了芯片面积。无缓冲偏转路由消除了路由器的输入端口缓冲区，在提供与现有缓冲路由相似的性能的同时，可以显著地帮助节省能源和芯片面积，特别是对于低到中等网络负载。然而，当拥塞增加时，无缓冲区经常导致微片偏转，以及导致网络性能下降的错误路由。在本文中，我们提出了注入速率节流(IRT)，这是一种局部节流机制，可以减少高负载无缓冲网络的偏转和误路由。IRT为每个网络节点提供独立的注入速率控制，从而减少网络拥塞。基于周期精确模拟器的仿真结果表明，与传统的无缓冲路由相比，IRT的平均传输时延降低了8.65%。
As the number of core integration on a single die grows, buffers consume significant energy, and occupy chip area. A bufferless deflection routing that eliminates router's input-port buffers can considerably help saving energy and chip area while providing similar performance of existing buffered routing, especially for low-to-medium network loads. However when congestion increases, the bufferless frequently causes flits deflections, and misrouting leading to a degradation of network performance. In this paper, we propose IRT(Injection Rate Throttling), a local throttling mechanism that reduces deflection and misrouting for high-load bufferless networks. IRT provides injection rate control independently for each network node, allowing to reduce network congestion. Our simulation results based on a cycle-accurate simulator show that using IRT, IRT reduces average transmission latency by 8.65% compared to traditional bufferless routing.