AutoSA: A Polyhedral Compiler for High-Performance Systolic Arrays on FPGA
AutoSA: A Polyhedral Compiler for High-Performance Systolic Arrays on FPGA
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DOI：
10.1145/3431920.3439292
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发表时间：
2021-02
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通讯作者：
Jie Wang;Licheng Guo;J. Cong
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作者：
Jie Wang;Licheng Guo;J. Cong
虽然脉动阵列架构有潜力提供极高的性能，但为目标应用定制高效的脉动阵列处理器却极具挑战性。设计脉动阵列需要了解应用的高层特性和底层硬件细节，因此这是一个要求苛刻且效率低下的过程。为了将用户从手动迭代的试错过程中解放出来，我们提出了AutoSA，这是一个用于在FPGA上生成脉动阵列的端到端编译框架。AutoSA基于多面体框架，并进一步在不同维度上结合了一系列优化以提高性能。它进行了高效且全面的设计空间探索以寻找高性能的设计。我们已经在广泛的应用中展示了AutoSA，在这些应用中，AutoSA在短时间内实现了高性能。例如，对于矩阵乘法，AutoSA在赛灵思Alveo U250上的浮点、16位和8位整数数据类型中分别达到了934 GFLOP、3.41 TOP和6.95 TOP。
While systolic array architectures have the potential to deliver tremendous performance, it is notoriously challenging to customize an efficient systolic array processor for a target application. Designing systolic arrays requires knowledge for both high-level characteristics of the application and low-level hardware details, thus making it a demanding and inefficient process. To relieve users from the manual iterative trial-and-error process, we present AutoSA, an end-to-end compilation framework for generating systolic arrays on FPGA. AutoSA is based on the polyhedral framework, and further incorporates a set of optimizations on different dimensions to boost performance. An efficient and comprehensive design space exploration is performed to search for high-performance designs. We have demonstrated AutoSA on a wide range of applications, on which AutoSA achieves high performance within a short amount of time. As an example, for matrix multiplication, AutoSA achieves 934 GFLOPs, 3.41 TOPs, and 6.95 TOPs in floating point, 16-bit and 8-bit integer data types on Xilinx Alveo U250.