Modeling Gather and Scatter with Hardware Performance Counters for Xeon Phi
Modeling Gather and Scatter with Hardware Performance Counters for Xeon Phi
复制标题
使用 Xeon Phi 的硬件性能计数器对收集和分散进行建模
DOI：
10.1109/ccgrid.2015.59
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发表时间：
2015
期刊：
影响因子：
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通讯作者：
Satoshi Matsuoka
中科院分区：
文献类型：
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作者：
James Lin;Akira Nukada;Satoshi Matsuoka
用于至强融核的英特尔初始众核指令（IMCI）引入了硬件实现的聚集和分散（G/S）功能，可将SIMD寄存器的内容从非连续内存位置加载/存储到非连续内存位置。然而，它们可能是Xeon Phi的关键性能瓶颈之一。建模G/S可以提供对Xeon Phi性能的深入了解，但是，现有的解决方案需要手写的组装实现。因此，我们用硬件性能计数器对G/S进行建模，这些计数器可以通过PAPI等工具进行分析。我们将地址生成互锁（AGI）事件描述为G/S的数目，用VPU_DATA_READ估计G/S的平均延迟，并将它们结合起来来建模G/S的总延迟。我们将我们的模型应用于3D 7点模板，结果显示G/S花费了近40%的总内核时间。我们还通过实现一个带有intrinsic的无G/S版本来验证该模型。的贡献的工作是一个性能模型的G/S建立与硬件计数器。我们相信该模型也可以普遍适用于CPU。
Intel Initial Many-Core Instructions (IMCI) for Xeon Phi introduces hardware-implemented Gather and Scatter (G/S) load/store contents of SIMD registers from/to non-contiguous memory locations. However, they can be one of key performance bottlenecks for Xeon Phi. Modelling G/S can provide insights to the performance on Xeon Phi, however, the existing solution needs a hand-written assembly implementation. Therefore, we modeled G/S with hardware performance counters which can be profiled by the tools like PAPI. We profiled Address Generation Interlock (AGI) events as the number of G/S, estimated the average latency of G/S with VPU_DATA_READ, and combined them to model the total latencies of G/S. We applied our model to the 3D 7-point stencil and the result showed G/S spent nearly 40% of total kernel time. We also validated the model by implementing a G/S- free version with intrinsics. The contribution of the work is a performance model for G/S built with hardware counters. We believe the model can be generally applicable to CPU as well.