W-Band CMOS 4-Bit Phase Shifter for High Power and Phase Compression Points
W-Band CMOS 4-Bit Phase Shifter for High Power and Phase Compression Points
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DOI：
10.1109/tcsii.2014.2362732
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发表时间：
2015-01-01
影响因子：
4.4
通讯作者：
Min, Byung-Wook
中科院分区：
文献类型：
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作者：
Lee, Hyo-Sung;Min, Byung-Wook
CMOS 4位移相器设计用于w波段应用，采用65nm CMOS工艺。开关延迟型90度、45度和22.5度1位移相器设计为使用信号线偏置电压具有高功率处理能力。分析了90度移相器、45度移相器和22.5度移相器的功率压缩和相位压缩，并针对大功率和相位压缩点对移相器进行了最佳级联。在77 GHz时，4位移相器的插入损耗为-25 +/- 2.1 dB， 16种不同相位的RMS增益误差为1.1 dB。在70 ~ 85ghz时，输入输出回波损耗小于- 8db。移相器在77 GHz时的均方根相位误差为7.2度，在75 ~ 85 GHz时的均方根相位误差小于11.25度。测量到的16种不同相态的最小1db功率压缩点为15.0 dBm。高输入功率也压缩了相位调整范围，增加了相位误差，在输入功率为21 dBm时，相位误差被限制在11.25度。移相器不消耗直流电流，芯片面积很小，0.122 mm(2)，不包括焊盘。
A CMOS 4-bit phase shifter is designed for W-band applications using a 65-nm CMOS process. Switched-delay-type 90 degrees, 45 degrees, and 22.5 degrees 1-bit phase shifters are designed to have high power-handling capability using a signal line bias voltage. The power and phase compression of 90 degrees, 45 degrees, and 22.5 degrees phase shifters are analyzed, and the phase shifters are optimally cascaded for high power and phase compression points. The measured insertion loss of the 4-bit phase shifter is -25 +/- 2.1 dB, and the root mean square (RMS) gain error of the 16 different phase states is 1.1 dB at 77 GHz. An input and output return loss is less than -8 dB at 70-85 GHz. The phase shifter has the RMS phase error of 7.2 degrees at 77 GHz and is less than 11.25 degrees at 75-85 GHz. The measured minimum 1-dB power compression point of 16 different phase states is 15.0 dBm. The high input power also compresses the phase adjustment range and increases the phase error, which is limited to 11.25 degrees up to the input power of 21 dBm. The phase shifter consumes no dc current and occupies a small chip area of 0.122 mm(2), excluding pads.