A New Family of High.Performance Parallel Decimal Multipliers
A New Family of High.Performance Parallel Decimal Multipliers
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DOI：
10.1109/arith.2007.6
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发表时间：
2007-06
期刊：
影响因子：
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通讯作者：
Álvaro Vázquez;E. Antelo;P. Montuschi
中科院分区：
文献类型：
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作者：
Álvaro Vázquez;E. Antelo;P. Montuschi
本文介绍了两种新颖的并行十进制乘法器结构。我们的乘法器基于一种新的小数进位保存多操作数加法算法，该算法使用了一种新的BCD-4221十进制位重新编码。与以前的方案相比，它显著改善了部分乘积约简树的面积和延迟。我们还提出了三种快速高效地并行生成部分积的方案。使用新的编码器将BCD-8421乘法器操作数重新编码为最小冗余的带符号位基-10、基-4和基-5表示，降低了部分乘积生成的复杂性。此外，SD基数-4和基数-5编码允许重复使用传统的并行二进制基-4乘法器来执行组合的二进制/十进制乘法。评估结果表明，与传统的Booth基4和基8并行二进制乘法器以及其他具有代表性的十进制乘法器相比，所提出的结构具有有趣的面积延迟特性。
This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry-save multioperand addition that uses a novel BCD-4221 recoding for decimal digits. It significantly improves the area and latency of the partial product reduction tree with respect to previous proposals. We also present three schemes for fast and efficient generation of partial products in parallel. The recoding of the BCD-8421 multiplier operand into minimally redundant signed-digit radix-10, radix-4 and radix-5 representations using new recoders reduces the complexity of partial product generation. In addition, SD radix-4 and radix-5 recodings allow the reuse of a conventional parallel binary radix-4 multiplier to perform combined binary/decimal multiplications. Evaluation results show that the proposed architectures have interesting area-delay figures compared to conventional Booth radix-4 and radix-8 parallel binary multipliers and other representative alternatives for decimal multiplication.