Formulation and Heuristic Algorithms for Multi-Chip Module Substrate Testing
Formulation and Heuristic Algorithms for Multi-Chip Module Substrate Testing
复制标题
多芯片模块基板测试的制定和启发式算法
DOI:
10.1016/j.compeleceng.2012.12.020
复制
发表时间:
2013
影响因子:
4.3
通讯作者:
Keisuke Murakami
中科院分区:
文献类型:
--
作者:
Shimada;Y.;重田祥範・荻原悠季;Keisuke Murakami
Multi-chip module (MCM) substrates are designed for packing two or more semiconductor chips. On these substrates, there are open faults in the wiring, which are electrical disconnections. We must therefore test the substrates to detect open faults, and it is essential to establish an efficient method of testing them. One type of test method uses two probes. Two probes, each touching one edge (end) of an inter-chip wiring, are used to check for the presence of faults. Testing is complete when we have confirmed that no faults exist on the MCM substrate. The objective is to minimize the time to complete testing, that is, our aim is to design efficient routes for the two probes. In this paper, we propose a novel approach of formulating the routing problem as a shortest path problem with covering constraints (SPCC) and we also propose three algorithms for the SPCC. In computational experiments, we show that our formulation and algorithms outperform the existing method.