Process variation mitigation via post silicon clock tuning
Process variation mitigation via post silicon clock tuning
复制标题
通过硅后时钟调整缓解工艺变化
DOI：
10.1145/1531542.1531598
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发表时间：
2009
期刊：
影响因子：
--
通讯作者：
S. Kundu
中科院分区：
文献类型：
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作者：
K. Nagaraj;S. Kundu
制造过程拐角、电压和温度（PVT）条件导致路径延迟和时钟偏差的变化。这种变化最终会降低制造芯片的性能。由于这种变化在预硅阶段很难预测，可调时钟缓冲器已在几种微处理器设计中使用。这些缓冲器被调优以最大限度地提高设计的工作时钟频率。在本文中，我们报告了一项关于在选定模式上使用测量延迟来确定应该针对哪个缓冲区进行调优的研究。基于统计仿真研究，发现该方法在平均情况下可将时钟频率提高9%。
Manufacturing process corner, voltage and temperature (PVT) conditions lead to variation in path delays and clock skews. Such variations end up degrading the performance of manufactured chips. Since, such variations are hard to predict in pre-silicon phase, tunable clock buffers have been used in several microprocessor designs. These buffers are tuned to maximize operating clock frequency of a design. In this paper, we report a study on using measured delays on selected patterns to determine which buffers should be targeted for tuning. Based on statistical simulation studies, it is found that the proposed approach can improve clock frequency by as much as 9% in the average case.