Optimising apodized grating couplers in a pure SOI platform to-0.5 dB coupling efficiency
Optimising apodized grating couplers in a pure SOI platform to-0.5 dB coupling efficiency
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DOI：
10.1364/oe.23.016289
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发表时间：
2015-06-15
期刊：
影响因子：
3.8
通讯作者：
Andreani, Lucio Claudio
中科院分区：
文献类型：
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作者：
Bozzola, Angelo;Carroll, Lee;Andreani, Lucio Claudio
我们通过通用变异方法，对“纯”绝缘体上硅 (SOI) 架构（即没有任何底部反射器元件）中的一维变迹光栅耦合器进行了理论优化。我们对 220 nm SOI 中的啁啾和变迹光栅耦合器进行了全面的 2D 有限差分时域研究，并证明该平台的全局最大耦合效率上限为 65% (-1.9 dB)。转向更厚硅层的设计，我们发现了 340 nm SOI 的新设计记录，模拟耦合效率为 89% (-0.5 dB)。采用更厚的硅层并不能进一步提高效率，这意味着 -0.5 dB 可能是不带底部反射器的 SOI 中光栅耦合器的全局最大值。即使考虑到 193 nm 紫外光刻制造限制，340 nm 设计仍然提供 -0.7 dB 的效率。这些新的变迹设计是首款与深紫外光刻兼容的纯 SOI 耦合器，可提供优于 -1 dB 的插入损耗。只需对现有沉积和光刻配方进行很小的改变，它们就可以与硅光子代工厂已经提供的多项目晶圆运行兼容。 (C) 2015年美国光学学会
We present a theoretical optimisation of 1D apodized grating couplers in a "pure" Silicon-On-Insulator (SOI) architecture, i.e. without any bottom reflector element, by means of a general mutative method. We perform a comprehensive 2D Finite Difference Time Domain study of chirped and apodized grating couplers in 220 nm SOI, and demonstrate that the global maximum coupling efficiency in that platform is capped to 65% (-1.9 dB). Moving to designs with thicker Si-layers, we identify a new record design in 340 nm SOI, with a simulated coupling efficiency of 89% (-0.5 dB). Going to thicker Si layers does not further improve the efficiency, implying that -0.5 dB may be a global maximum for a grating coupler in SOI without a bottom-reflector. Even after allowing for 193 nm UV-lithographic fabrication constraints, the 340 nm design still offers -0.7 dB efficiency. These new apodized designs are the first pure SOI couplers compatible with deep-UV lithography to offer better than -1 dB insertion losses. With only very minor changes to existing deposition and lithography recipes, they are compatible with the multi-project wafer runs already offered by Si-Photonics foundries. (C) 2015 Optical Society of America