An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs
An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs
复制标题
可调延迟缓冲器的优化分配算法和多功耗模式设计中时钟偏差优化的实用扩展
DOI：
10.1109/tcad.2012.2220769
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发表时间：
2013
影响因子：
2.9
通讯作者：
Taewhan Kim
中科院分区：
文献类型：
--
作者：
Kyoung;Deokjin Joo;Taewhan Kim
满足时钟倾斜约束是时钟树合成中最重要的任务之一。此外，当时钟树设计在多功率模式环境下时，由于施加在某些设计模块上的电压随着功率模式的变化而变化，该任务变得更加难以解决。近年来，可调延迟缓冲器（ADB）的研究表明，它的延迟可以动态调整，可以有效地解决多种功率模式下的时钟倾斜问题。但是，由于adb的面积或控制开销，尽量减少要分配的adb数量是非常重要的。本文提供了在多种功率模式下使用ADBs进行时钟偏差优化的完整解决方案。我们提出了一种线性时间算法，同时解决了计算问题：1)要使用的adb的最小（最优）数量；2)每个ADB的放置位置；3)分配给各电源模式的各ADB的延时值。实验结果表明，与之前迭代执行ADB分配，放置和值分配的工作相比，我们的集成算法在所有测试基准上都产生了一致的更好的设计；在30- 50ps的倾斜界下，即使与以前的ADB分配、放置和延迟分配算法相比，时钟延迟更短，它也平均减少了9.27%的ADB数量。为了使其在实践中可行，我们还提出了一种新的ADB设计技术和系统算法解决方案，以解决离散延迟值，转换率变化，非零初始ADB延迟以及ADB调整大小的可能探索等问题。
Satisfying a clock skew constraint is one of the most important tasks in clock tree synthesis. Moreover, the task becomes much harder to solve when the clock tree is designed in a multiple power mode environment, in which the voltage applied to some design module varies as the power mode changes. Recently, it has been shown that an adjustable delay buffer (ADB), whose delay can be tuned dynamically, can be used to solve the clock skew problem effectively under multiple power modes. However, due to the area or control overhead by ADBs, it is very important to minimize the number of ADBs to be allocated. This paper provides a complete solution to the problem of clock skew optimization using ADBs under multiple power modes. We propose a linear-time algorithm that simultaneously solves the problems of computing: 1) the minimum (optimal) number of ADBs to be used; 2) the location where each ADB is to be placed; and 3) the delay value of each ADB to be assigned to each power mode. Experimental results show that, in comparison with the previous work, which iteratively performs the ADB allocation, placement, and value assignment, our integrated algorithm produces consistently better designs for all tested benchmarks; it reduces the numbers of ADBs by 9.27% on average under the skew bound of 30-50 ps, even with shorter clock latencies compared to that of previous algorithm of ADB allocation, placement, and delay assignment. To make it practically feasible, we also propose a new ADB design technique and systematic algorithmic solutions to address the problems of discrete delay values, slew rate variation, nonzero initial ADB delay, and a possible exploration of ADB resizing.