An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating
An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating
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DOI：
10.1109/tvlsi.2015.2393914
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发表时间：
2016
影响因子：
2.8
通讯作者：
A. Bsoul;S. Wilton;K. H. Tsoi;W. Luk
中科院分区：
文献类型：
--
作者：
A. Bsoul;S. Wilton;K. H. Tsoi;W. Luk
泄漏功率是使用 90 纳米及更小技术节点构建的现场可编程门阵列 (FPGA) 总功耗的重要组成部分。功率门控被证明可以有效降低泄漏功率。以前的技术侧重于在配置时关闭未使用的 FPGA 资源；这种方法的好处取决于资源利用率。在本文中，我们提出了一种支持动态控制电源门控的 FPGA 架构，其中 FPGA 资源可以在运行时有选择地断电。对于具有较长闲置时间的模块的应用来说，这可能会带来显着的整体节能效果。我们还提出了一个 CAD 流程，可用于将应用程序映射到建议的架构。我们通过改变不同的 FPGA 架构参数和功率门控粒度来研究面积和功耗的权衡。所提出的 CAD 流程用于将一组具有多个电源门控模块的基准电路映射到所提出的架构。这些电路可实现高达 83% 的节能。最后，我们研究了用于内窥镜检查的机器人的控制系统。在此应用中，使用所提出的架构与时钟门控相结合可节省高达 19% 的能源。
Leakage power is an important component of the total power consumption in field-programmable gate arrays (FPGAs) built using 90-nm and smaller technology nodes. Power gating was shown to be effective at reducing the leakage power. Previous techniques focus on turning OFF unused FPGA resources at configuration time; the benefit of this approach depends on resource utilization. In this paper, we present an FPGA architecture that enables dynamically controlled power gating, in which FPGA resources can be selectively powered down at run-time. This could lead to significant overall energy savings for applications having modules with long idle times. We also present a CAD flow that can be used to map applications to the proposed architecture. We study the area and power tradeoffs by varying the different FPGA architecture parameters and power gating granularity. The proposed CAD flow is used to map a set of benchmark circuits that have multiple power-gated modules to the proposed architecture. Power savings of up to 83% are achievable for these circuits. Finally, we study a control system of a robot that is used in endoscopy. Using the proposed architecture combined with clock gating results in up to 19% energy savings in this application.