Implementation of a high precision multi-measurement time-to-digital convertor on a Kintex-7 FPGA
Implementation of a high precision multi-measurement time-to-digital convertor on a Kintex-7 FPGA
复制标题
在 Kintex-7 FPGA 上实现高精度多重测量时间数字转换器
DOI：
10.1016/j.nima.2018.02.064
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发表时间：
2018-05-21
影响因子：
1.4
通讯作者：
Liu, Chong
中科院分区：
文献类型：
--
作者：
Kuang, Jie;Wang, Yonggang;Liu, Chong
基于现场可编程门阵列(现场可编程门阵列)的时间数字转换器(TDC)越来越受到人们的青睐。多点测量是突破信元时延限制提高TDC精度的有效方法。然而，在28 nm和更先进工艺的现场可编程门阵列上实现多测量的TDC面临着新的挑战。借鉴前面工作中提出的单计数器编码方案，我们在Xilinx KINTEX-7型现场可编程门阵列上实现了环形振荡器多测量TDC。使用两个TDC通道测量0 ns-30 ns范围内的时间间隔，平均均方根精度可提高到5.76 ps，而逻辑资源使用量与单测量TDC相同，TDC死区时间仅为22 ns。研究表明，多种测量方法仍然适用于当前主流的现场可编程门阵列。此外，本文的新实现能够更好地在时间精度、资源使用和TDC死区时间之间进行权衡。
Time-to-digital convertors (TDCs) based on field programmable gate array (FPGA) are becoming more and more popular. Multi-measurement is an effective method to improve TDC precision beyond the cell delay limitation. However, the implementation of TDC with multi-measurement on FPGAs manufactured with 28 nm and more advanced process is facing new challenges. Benefiting from the ones-counter encoding scheme, which was developed in our previous work, we implement a ring oscillator multi-measurement TDC on a Xilinx Kintex-7 FPGA. Using the two TDC channels to measure time-intervals in the range (0 ns-30 ns), the average RMS precision can be improved to 5.76 ps, meanwhile the logic resource usage remains the same with the one-measurement TDC, and the TDC dead time is only 22 ns. The investigation demonstrates that the multi-measurement methods are still available for current main-stream FPGAs. Furthermore, the new implementation in this paper could make the trade-off among the time precision, resource usage and TDC dead time better than ever before.